1. Field of the Invention
The present invention generally relates to a semiconductor device, and in particular, to a semiconductor device with memories and a method for memory tests which tests the memory.
2. Description of the Related Art
In general, semiconductor storage devices include a built-in ECC circuit type storage device. “ECC” stands for “error correcting code” in some cases. In the present specification, “ECC” is used to mean “error checking and correcting.” Both a data memory for storing data and a code memory for storing ECC codes are incorporated in the built-in ECC circuit type semiconductor storage device (refer to, for example, U.S. Pat. No. 6,295,617).
For such a semiconductor storage device, a method for memory tests is available which tests the memories utilizing a built-in test circuit and the ECC circuit (refer to, for example, Japanese Patent No. 2001-351398).
With the method for memory tests described in this prior art document, when a memory read speed is tested, a 1-bit inversion circuit is used to invert a predetermined bit in write data and in an ECC code. Then, the data containing the error bits is written in memory cells. Test conditions are set so that during a read, the ECC circuit checks and corrects the errors in the data.
With the conventional method for memory tests, both the data memory and the code memory must be tested. Thus, compared to tests on a single memory which are executed only on the data memory of the same capacity, the conventional method requires a longer time for the test process. Furthermore, test circuits are required which deal with the data memory and code memory, respectively. This increases test costs.